"Thermo-structural Model of Stacked Field-programmable Gate Arrays (FPGAs) with Through-silicon Vias (TSVs)", C. Zhang, A. Dasu and L. Li. Accepted to IET/IEE Electronics Letters. Impact factor: 1.01. pdf(Author's pre-print copy). (Abstract)

Publications In Review

Numerical Analysis of Thermo-mechanical Reliability of Through Silicon Vias (TSVs) and Solder interconnects in 3-dimensional Integrated Circuits (Submitted to Microelectronic Engineering)

AUTHORS - Leila J. Ladani, Omar Rodriguez

ABSTRACT - 3-dimensional integrated circuit (3D IC) is a promising technology in today’s IC packaging industry. Since the technology is in its infancy stages, many aspects of this technology are still under heavy investigation. Reliability of through silicon vias (TSV) and interlayer bonds are issues that are more complicated in 3D ICs, compared to conventional planar packages, due to complexity of the architecture and miniaturized interconnects. Optimizing design of these packages is essential in order to avoid short fatigue life of interconnects. This manuscript addresses the impact of design parameters such as die thickness, TSV diameter and pitch, underfill thickness and underfill stiffness on thermo-mechanical reliability of Direct Chip Attach (DCA) solder joints and TSVs used in a 3D IC packages. A design was proposed where DCA was used to connect 4 layers of ICs and TSVs were used to connect the active layers of silicon dies. Solder joints, as small as 50-micron diameter, were used to attach silicon layers. A numerical experiment was designed to vary these factors at 3 levels using an L9 orthogonal array. A 3-dimensional model of the package was built and solved under thermal cycling. Solder is considered as visco-plastic material and copper interconnects are assumed to follow bi-linear isotropic hardening behavior. Two continuum damage models; Energy Partitioning (E-P) and Coffin-Manson were used to assess the number of cycles to failure for solder joints and TSV copper interconnects respectively. Minitab software was used to analyze the results of the experiment and General Linear Model Analysis of Variance (GLMANOVA) was used to evaluate the significance of each factor. The most influential factors on the thermo-mechanical reliability of solder interconnects were found to be underfill stiffness and height. However, the most influential factor on TSV reliability was found to be TSV diameter. A non-linear response was observed for TSV pitch and diameter indicating that the optimum level was in the range selected. Locations of failures were found to depend on selected parameters and effective CTE. An analytical function was developed to estimate the effective CTE for silicon layers containing TSVs as function of TSVs diameter and pitch. These two parameters can be varied to obtain the desired CTE and vary the location of failures.

Thermo-mechanical Stress Analysis of Solid-liquid-inter-diffusion bonds in 3-dimensional Integrated Circuits (Submitted to IEEE TDMR)

AUTHOR - Leila J. Ladani

ABSTRACT - A simplified structural analysis approach is presented to evaluate the thermo-mechanical stress in layered structures of electronic packages using effective properties of composite layers and tri-material stress analysis. This approach is utilized to estimate interfacial peeling and shear stresses at the interconnect layer for a 3-dimensional integrated circuit package fabricated using SLID bonds. To evaluate effect of design parameters on stress and life of the interconnects a numerical experiment is designed and implemented by varying factors such as die thickness, bond size, underfill properties, and substrate thickness at 3 levels. Stresses at copper interconnect are calculated using the analytical approach for all the treatments of experiment. A finite element model was built and same experiment was applied to determine the interfacial stress in copper interconnects and stress in SLID bonds for all the treatments. Comparison of the results for stress in copper interconnects at the interface shows the same trend in main effect in both finite element and analytical approach validating the analytical approach. This analysis shows that die and substrate thicknesses are the most influential factors among the selected parameters on stress at the interface and on copper interconnects. Main effect results for stress analysis in SLID bonds using finite element shows that die thickness and underfill stiffness are the most influential factors in defining stress at SLID bonds. Both factors show higher stress at higher levels.

A Thermal-mechanical Coupled Finite Element Model With Experimental Temperature Veri cation For Vertically Stacked FPGAs (Submitted to Microelectronic Engineering)

AUTHORS - Chunbo (Sam) Zhang, Ramachandra Kallam, Andrew Deceuster, Aravind Dasu, Leijun Li

ABSTRACT - Back end of line 3D integration of dies is a promising technology that can allow for considerable boost in inter-chip communication and reduction in form factor of a package. This can result in, however, high die temperatures, particularly for multi-tier FPGAs, due to the high density of power dissipating circuits. Therefore, to design thermally aware multi-tier FPGAs, there is a need to rst understand the relationship among circuit architectures, toggle rates, layout, clock frequency, I/O behavior, power, temperature, thermal stress, and thickness of inter-die substrates. This study investigated the relationship among these parameters as tested on a Spartan 3E-250K FPGA. The power-temperature simulations have been conducted on a model built in ANSYS nite element package. The model predictions have been verified by thermocouple-measured case temperatures. The verified model has been extended to predict the temperature and stress distributions for a 2-tier, stacked package. Key words: Thermo-Mechanical Modeling, Finite Element, 3-Dimensional Fields, ICs, FPGAs